Semiconductor memory device
US12198767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2023 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Sep 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.