Memory chip test method and apparatus, medium, and device
US12198773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2023 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jul 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip test method includes: a mode register write command is sent to a memory chip to control a memory chip to enter a test mode of Write Clock to clock leveling (Wck2ck Leveling); a first preset time is set, and a read and write clock signal is sent to the memory chip after waiting for the first preset time; a predicted value of the Wck2ck Leveling is determined according to the first preset time and a system clock cycle; after sending the read and write clock signal and waiting for a second preset time, a test data output port of the memory chip is detected to obtain a test value; and the test value and the predicted value are compared to determine whether the memory chip is abnormal. A method for testing a Wck2ck Leveling function is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.