Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure
US12198932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2021 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Mar 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.