Packaging structure and method for preparing same
US12198942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2021 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | May 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a chip packaging structure and a method for preparing the same. The packaging structure includes a glass substrate, metal connecting posts, a first packaging layer, a connection layer, semiconductor chips, a filler layer, a second packaging layer, a controlled collapse chip connection (C4) layer, a base substrate, and a heat sink housing. In the present disclosure, metal connecting posts are pre-formed in a glass substrate, so that the glass substrate serves as an intermediate conduction layer, and the semiconductor chips and the C4 layer are respectively formed at opposite ends of the metal connecting posts to perform electrical connections, so that the number of process steps for preparing the packaging structure is minimized and the manufacturing cost is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.