Semiconductor circuit including latch circuit for error correction
US12199613B2 · kind B2 · utility
0Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2021 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Nov 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.