Parallel-to-serial conversion circuit, parallel-to-serial conversion circuit layout, and memory
US12199645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jul 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.