Software-defined compute nodes on multi-SoC architectures
US12199838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2023 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Apr 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are methods for forming redundant node configurations in a multi-systems-on-a-chip environment. Each system-on-a-chip can include one or processors and memories independent of other systems-on-a-chip and in communication via a cache coherent fabric. To facilitate rapid and extensible reconfiguration, various systems-on-a-chip from the multi-systems-on-a-chip environment can be configured into a redundant node configuration, with each logical node implemented by one or more of the systems-on-a-chip. Each system-on-a-chip within a logical node can be configured to utilize a shared memory space, such as by transparent mirroring of logical memory addresses. Across nodes, systems-on-a-chip can communicate using a device-to-device protocol such as a non-transparent bridge. My reconfiguration of communication between systems-on-a-chip, the multi-systems-on-a-chip environment can be reconfigured to represent a variety of redundant configurations. In one example, a multi-systems-on-a-chip environment can be configured to support safe, resilient operation of an autonomous vehicle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.