Memory device structure and manufacturing method thereof
US12200943B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Aug 2, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Aug 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
Abstract
A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.