Integrated circuit with debugger and arbitration interface
US12204393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Nov 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.