Memory processing unit architecture mapping techniques
US12204447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jan 28, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory processing unit (MPU) configuration method can include mapping operations of one or more neural network models to sets of cores in a plurality of processing regions. In addition, dataflow of the one or more neural network models can be mapped to the sets of cores in the plurality of processing regions. Furthermore, configuration information can be generated based on the mapping of the operations of the one or more neural network models to the set of cores in the plurality of processing regions and the mapping of dataflow of the one or more neural network models to the sets of cores in the plurality of processing regions. The method can be implemented by generating an initial graph from a neural network model. A mapping graph can then be generated from the final graph. One or more configuration files can then be generated from the mapping graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.