Integration of disparate system architectures using configurable isolated memory regions and trust domain conversion bridge
US12204463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jan 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.