Communication logic to enhance area effectiveness for memory repair mechanism
US12204782B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 20, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jul 31, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.