Victim row counters in memory devices
US12205626B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 29, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | May 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some examples, a memory device includes a plurality of rows of memory cells, a plurality of victim counters associated with respective rows of memory cells of the plurality of rows of memory cells, and a plurality of aggressor counters associated with the respective rows of memory cells. A first victim counter of the plurality of counters is associated with a first row of the plurality of rows of memory cells, the first victim counter to advance in response to advances in counts of aggressor counters associated with neighboring rows of memory cells that are neighbors of the first row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.