Symmetric memory cell and BNN circuit
US12205630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2020 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Feb 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01742
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.