Patent · US Active

Write assist circuit for static random-access memory (SRAM)

US12205636B2 · kind B2 · utility

0Cited by
8References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 2, 2023
Grant dateJan 21, 2025
Priority date
Expiry dateJul 21, 2043

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C11/412
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.