Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same
US12205668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jul 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.