Conductivity reducing features in an integrated circuit
US12205942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Nov 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.