Cell structure of silicon carbide MOSFET device, and power semiconductor device
US12205991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2020 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
Abstract
A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.