LDMOS device and method for preparation thereof
US12205996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2020 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Sep 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/01
Abstract
The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.