Memory devices
US12207473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Nov 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.