Pixel arrangement structure, display panel, and display device
US12207517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | May 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/166
Abstract
A pixel arrangement structure includes two first sub-pixels and two second sub-pixels which are connected as a first virtual quadrilateral. The two first sub-pixels are located at two first vertices of the first virtual quadrilateral. The two second sub-pixels are located at two second vertices of the first virtual quadrilateral. The two first vertices and the two second vertices are alternately arranged and spaced apart from each other. A third sub-pixel is located within the first virtual quadrilateral, and a center of the third sub-pixel deviates from a center of the first virtual quadrilateral. In a row direction or a column direction, the first virtual quadrilateral includes a first side and a second side facing to each other, and a length of the first side is smaller than a length of the second side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.