Array substrate and method for manufacturing same, and display device
US12210255B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136213
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is an array substrate. The array substrate includes a base substrate, a gate line, a data line, a discharge line, a first pixel electrode, a first thin film transistor, a second thin film transistor and a first connection line. A control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both connected to the gate line. The first electrode of the first thin film transistor is connected to the data line. Both the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are connected to the first pixel electrode by the first connection line. The second electrode of the second thin film transistor is connected to the discharge line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.