Single-clock insertion sort scheme
US12210371B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | May 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sorting circuit includes: a stack of registers for storing a set of data values from a highest value to a lowest value; a set of comparators for substantially simultaneously comparing an input data value to the set of data values stored in the registers, where the comparators enable registers whose stored data values are less than the input data values to receive a replacement data value; and a set of multiplexers, each associated with a register in the stack to select the replacement data value when the register is enabled. The multiplexer selects the input data value to be the replacement data value if the register is the highest register in the stack currently storing a data value that is less than the input data value. Otherwise, the multiplexer selects the data value stored in the next-highest register in the stack to be the replacement data value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.