Deterministic hardware indictment in response to fatal PCIe ntb error
US12210409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Aug 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0769
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deterministic hardware indictment process is used to indict one Compute Node (CN) of a pair of CNs in response to occurrence of a fatal error on a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) interconnecting the two CN. Status information is exchanged between the CNs on a communication medium that is separate from the NTB. The indictment process is run locally on each CN based on whatever information is available to the CN. When the CN does not receive status information from the other CN, the CN runs a self-indictment check. When status information is received, and only one CN reports an error, the indictment process indicts the compute node that reported the error. If both CNs report errors, an error severity comparison process is used to select a CN to be indicted. If the reported errors are equally severe, a default CN is indicted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.