Patent · US Active

Memory controller for improving data integrity and providing data security and a method of operating thereof

US12210633B2 · kind B2 · utility

0Cited by

1References

18Claims

0Family size

Assignee

SKYECHIP SDN BHD · MY

Inventors

Yu Ying Ong · Ampang Jaya, MY
Muhamad Aidil Jazmi · Bayan Lepas, MY
Soon Chieh Lim · Merang, MY
Chee Hak Teh · Kampung Bukit Kechil, MY

Key dates

Filing date	Feb 18, 2021
Grant date	Jan 28, 2025
Priority date	—
Expiry date	Nov 13, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/64
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.