Modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data content
US12210754B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.