Semiconductor memory device
US12211557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Aug 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.