Dynamic gate steps for last-level programming to improve write performance
US12211563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.