Memory system with verify operations of odd and even word lines
US12211567B2 · kind B2 · utility
1Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jan 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.