Integrated circuit devices having highly integrated NMOS and PMOS transistors therein and methods of fabricating the same
US12211847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2021 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Oct 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.