Array substrate and manufacturing method therefor, and display panel
US12211854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/103
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a substrate; a gate disposed on the substrate; a first insulating layer covering the gate; a first semiconductor layer and a second semiconductor layer that are provided on the first insulating layer, a channel corresponding to the gate being provided in the first semiconductor layer and second semiconductor layer, the second semiconductor layer including a first metal oxide semiconductor layer and a second metal oxide semiconductor layer which are stacked, both the first metal oxide semiconductor layer and the second metal oxide semiconductor layer being disconnected at the channel, and the oxygen vacancy concentration of the second metal oxide semiconductor layer being less than the oxygen vacancy concentration of the first metal oxide semiconductor layer; and a source and a drain that are provided on the second semiconductor layer, both the source and the drain being in electrically conductive contact with the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.