Gate-all-around transistor with strained channels
US12211897B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 31, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.