Process, voltage, and temperature invariant time-to-digital converter with sub-gate delay resolution
US12212324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A control circuit and a method for delaying an electronic signal are provided, along with a time-to-digital converter including the control circuit. The example control circuit includes a first delay circuit having a first plurality of delay elements electrically connected in series and configured to generate a first control voltage associated with a first delay time. The control circuit further includes a second delay circuit having a second plurality of delay elements electrically connected at least in part in series. The second delay circuit is configured to generate a second control voltage associated with a second delay time. A first group of delay elements within the second plurality of delay elements exhibits the first delay time based on the first control voltage, and a second group of the second plurality of delay elements exhibits a second delay time based at least in part on the second control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.