Analog-to-digital convertors positioned on a single semiconductor die
US12212331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Apr 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.