Transceiver device for array signal processing
US12212387B2 · kind B2 · utility
0Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0491
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Transceiver integrated circuit suitable for distributed placement across an active antenna unit. ICs with two serial data ports configured to transmit and receive aggregated signal-port IQ data packets with adjacent ICs within a subarray of ICs, or to a beamformer processor. A packet header inspection circuit may identify aggregated signal-port IQ data packets for local processing, and identify received aggregated signal-port IQ data packets for processing by another device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.