Power efficient circuits and methods for phase alignment
US12212646B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 27, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jan 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.