Array substrate and method for manufacturing the same, and display apparatus
US12216365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.