Draining operation for draining dirty cache lines to persistent memory
US12216589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2021 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Jan 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.