Substrate assembly
US12216873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2023 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Nov 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.