Memory device, memory system having the same and operating method thereof
US12217786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2024 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Mar 22, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.