Package structure
US12218082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2023 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Nov 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.