Array substrate and manufacturing method thereof
US12218143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2021 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Dec 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/423
Abstract
An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer. The array substrate includes a thin film transistor (TFT) area, and the second metal layer includes a source-drain metal sub-layer located in the TFT area. The TFT area is defined with an active layer exposed area. The array substrate includes a barrier layer, and an orthographic projection of the barrier layer on the active layer at least partially covers an orthographic projection of the active layer exposed area on the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.