Semiconductor device
US12218212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2023 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Oct 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.