Layer structure including dielectric layer, methods of manufacturing the layer structure, and electronic device including the layer structure
US12218217B2 · kind B2 · utility
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2References
26Claims
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Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Apr 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an anti-ferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.