Short-circuit fault detection method for a power grid
US12218500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2024 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | May 1, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J2300/24
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for analytically studying fault responses of an inverter-interfaced renewable energy source (IIRES). The IIRES includes a decoupled sequence control (DSC) system, and the DSC system includes a converter, a current controller, a low-voltage ride-through (LVRT) control unit, and positive and negative sequence components calculation (PNSCC) structures. The method includes: determining a detailed fault model of the IIRES; determining a unified model of the PNSCC structures; determining a simplified fault model of the IIRES in a fault detection phase; determining a simplified fault model of the IIRES in a control transient response (CTR) phase; detecting a short-circuit fault; cutting off an outer loop of the DSC system; switching the DSC system to a current control mode through the LVRT unit by the current controller; analyzing the short-circuit fault; and designing an enhanced fault-ride-through control of the IIRESs to suppress an inrush current to protect the IIRES.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.