Comparator circuit, method for correcting mismatch and memory
US12218673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2022 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Sep 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.