Clock recovery for PAM4 signaling using bin-map
US12218786B1 · kind B1 · utility
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3References
19Claims
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Key dates
| Filing date | Nov 21, 2022 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Mar 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.