Nonvolatile memory chip and semiconductor package including the same
US12219774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2021 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Apr 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.