Variable pitch fan-out routing for display panels having narrow borders
US12222611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2023 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Aug 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.