Array substrate, display panel, and display apparatus
US12222612B2 · kind B2 · utility
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2References
19Claims
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Key dates
| Filing date | May 13, 2021 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Apr 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0233
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.